Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy
US5327383A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1992 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Apr 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.