Method of erasure for a non-volatile semiconductor memory device
US5327385A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1993 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Feb 19, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method of erasure for a non-volatile semiconductor memory device having a floating gate. For a first time interval, a voltage having one polarity is applied to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of electrons from said floating gate through a tunneling oxide film. For a second time interval after said first time interval, a voltage having an opposite polarity to said one polarity is applied to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of electrons from a channel region of said memory device to said floating gate through said tunneling oxide film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.