Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
US5327540A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1993 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Feb 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.