Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right
US5327571A · kind A · utility
3Cited by
17References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1993 |
| Grant date | Jul 5, 1994 |
| Priority date | — |
| Expiry date | Aug 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.