Method for producing bipolar transistors having polysilicon contacted terminals
US5328856A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Aug 27, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention discloses a process by which a silicon bipolar transistor can be fabricated having a polysilicon emitter region and a polysilicon base region by a single polysilicon deposition step. After conventional fabrication of the substrate, collector and base layers, a first dielectric layer is deposited over the developing wafer structure. The first dielectric layer is then etched in order to define polysilicon emitter, base and collector regions. Next, a polysilicon layer is deposited over the first dielectric layer and the etched regions. A planarization layer is deposited over the polysilicon layer, and the planarization layer and the polysilicon layer are etched so that polysilicon only remains in the defined polysilicon emitter, base and collector regions. The polysilicon emitter, base and collector regions are then implanted with dopants to provide the appropriate interfaces. A second dielectric layer is deposited over the first dielectric layer and the polysilicon regions and is etched to open contacts to the polysilicon emitter, base and collector regions. A metallization layer is then deposited and etched to contact the polysilicon emitter, base and collector region…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.