Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions
US5328864A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1991 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | May 13, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.