Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure
US5329142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1992 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Aug 7, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.