Two transistor flash EPROM cell
US5329487A · kind A · utility
40Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1993 |
| Grant date | Jul 12, 1994 |
| Priority date | — |
| Expiry date | Mar 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.