Anil Gupta
98Patents
28h-index
130Co-inventors
91Inventor score
Filing activity: Feb 8, 1982 → Apr 16, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6230233A | Wear leveling techniques for flash EEPROM systems | Physics | 553 | Expired |
| US5430859A | Solid state memory system including plural memory chips and a serialized bus | Emerging Cross-Sectional Technologies | 550 | Expired |
| US6081447A | Wear leveling techniques for flash EEPROM systems | Physics | 374 | Expired |
| US6850443B2 | Wear leveling techniques for flash EEPROM systems | Physics | 331 | Expired |
| US6594183B1 | Wear leveling techniques for flash EEPROM systems | Physics | 290 | Expired |
| US6715044B2 | Device and method for controlling solid-state memory system | Emerging Cross-Sectional Technologies | 250 | Expired |
| US10027689B1 | Interactive infection visualization for improved exploit detection and signature generation for malware and malware families | Physics | 214 | Active |
| US10148693B2 | Exploit detection system | Electricity | 155 | Active |
| US5438573A | Flash EEPROM array data and header file structure | Physics | 151 | Expired |
| US5822245A | Dual buffer flash memory architecture with multiple operating modes | Physics | 144 | Expired |
| US5471478A | Flash EEPROM array data and header file structure | Physics | 127 | Expired |
| US10503904B1 | Ransomware detection and mitigation | Physics | 111 | Active |
| US5806070A | Device and method for controlling solid-state memory system | Emerging Cross-Sectional Technologies | 107 | Expired |
| US6317812A | Device and method for controlling solid-state memory system | Emerging Cross-Sectional Technologies | 97 | Expired |
| US6148363A | Device and method for controlling solid-state memory system | Emerging Cross-Sectional Technologies | 77 | Expired |
| US4511811A | Charge pump for providing programming voltage to the word lines in a semiconductor memory array | Physics | 66 | Expired |
| US5353248A | EEPROM-backed FIFO memory | Physics | 55 | Expired |
| US7353325B2 | Wear leveling techniques for flash EEPROM systems | Physics | 53 | Expired |
| US5247478A | Programmable transfer-devices | Electricity | 48 | Expired |
| US4546454A | Non-volatile memory cell fuse element | Electricity | 46 | Expired |
| US5475858A | Real time multiprocessor system having a write only data link connected to one of the ports of the memory of each of the processor nodes | Physics | 45 | Expired |
| US5329487A | Two transistor flash EPROM cell | Electricity | 40 | Expired |
| US6112271A | Multiconfiguration backplane | Physics | 38 | Expired |
| US6115761A | First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment | Physics | 32 | Expired |
| US6118705A | Page mode erase in a flash memory array | Physics | 32 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.