Method for electrically testing a semiconductor die using a test apparatus having an independent conductive plane
US5330919A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1993 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Feb 8, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for controlling a characteristic impedance during testing of a semiconductor die (13). The semiconductor die (13) is mounted in a TAB package (10 or 54 ) wherein the TAB package ( 10 or 54 ) lacks a ground plane. A conductive plate (40 or 70) is removably mounted to a test contact fixture ( 29 or 60 ) . The conductive plate (40 or 70) may be coated with a layer of dielectric material (50, 56, or 74) having a specified thickness. The layer of dielectric material (50, 56, or 74) contacts a plurality of conductive fingers (16). A microstrip transmission line is formed which includes the plurality of conductive fingers (16) , the layer of dielectric material (50, 56, or 74), and the conductive plate (40 or 70). The semiconductor die (13) is tested by a computer controlled automatic tester (28).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.