Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5330920A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1993 |
| Grant date | Jul 19, 1994 |
| Priority date | — |
| Expiry date | Jun 15, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.