Method of making a capacitor for an integrated circuit

US5330931A · kind A · utility

Assignees

• Nortel Networks Limited · CA
• McMaster University · CA

Inventors

• Ismail Emesh · Gilbert, US
• Iain D. Calder · Gatineau, CA
• Vu Q. Ho · Gatineau, CA
• Gurvinder Jolly · Mississauga, CA
• Lynnette D. Madsen · Ottawa, CA

Key dates

• Filing date: Sep 23, 1993
• Grant date: Jul 19, 1994
• Expiry date: Sep 23, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/682

Abstract

A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.