Multiple input frequency memory controller
US5333293A · kind A · utility
23Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1991 |
| Grant date | Jul 26, 1994 |
| Priority date | — |
| Expiry date | Sep 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.