Randy M. Bonella
34Patents
23h-index
26Co-inventors
81Inventor score
Filing activity: Sep 11, 1991 → Aug 14, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6317352A | Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules | Emerging Cross-Sectional Technologies | 370 | Expired |
| US6742098B1 | Dual-port buffer-to-memory interface | Physics | 347 | Expired |
| US6587912B2 | Method and apparatus for implementing multiple memory buses on a memory module | Physics | 322 | Expired |
| US6658509B1 | Multi-tier point-to-point ring memory interface | Physics | 283 | Expired |
| US6477614B1 | Method for implementing multiple memory buses on a memory module | Physics | 244 | Expired |
| US6487102B1 | Memory module having buffer for isolating stacked memory devices | Physics | 233 | Expired |
| US6625687B1 | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing | Emerging Cross-Sectional Technologies | 229 | Expired |
| US6553450B1 | Buffer to multiply memory interface | Emerging Cross-Sectional Technologies | 218 | Expired |
| US6493250B2 | Multi-tier point-to-point buffered memory interface | Physics | 158 | Expired |
| US7024518B2 | Dual-port buffer-to-memory interface | Physics | 129 | Expired |
| US5537555A | Fully pipelined and highly concurrent memory controller | Physics | 119 | Expired |
| US6747887B2 | Memory module having buffer for isolating stacked memory devices | Physics | 106 | Expired |
| US6820163B1 | Buffering data transfer between a chipset and memory modules | Physics | 105 | Expired |
| US6928571B1 | Digital system of adjusting delays on circuit boards | Physics | 91 | Expired |
| US6369605B1 | Self-terminated driver to prevent signal reflections of transmissions between electronic devices | Electricity | 87 | Expired |
| US5325503A | Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line | Physics | 87 | Expired |
| US5471590A | Bus master arbitration circuitry having improved prioritization | Physics | 70 | Expired |
| US6449213B1 | Memory interface having source-synchronous command/address signaling | Physics | 70 | Expired |
| US6530006B1 | System and method for providing reliable transmission in a buffered memory system | Physics | 65 | Expired |
| US6697888B1 | Buffering and interleaving data transfer between a chipset and memory modules | Physics | 51 | Expired |
| US5446863A | Cache snoop latency prevention apparatus | Physics | 44 | Expired |
| US6928593B1 | Memory module and memory component built-in self test | Physics | 28 | Expired |
| US5797020A | Bus master arbitration circuitry having improved prioritization | Physics | 24 | Expired |
| US5333293A | Multiple input frequency memory controller | Physics | 23 | Expired |
| US7941592B2 | Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells | Physics | 19 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.