Method of fabricating an integrated circuit with lines of critical width extending in the astigmatically preferred direction of the lithographic tool
US5334541A · kind A · utility
2Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1992 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | Dec 31, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/15
Abstract
A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.