Method of producing a scribelined layout structure for plastic encapsulated circuits
US5336456A · kind A · utility
13Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1992 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | Dec 15, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
A method of producing surface features having topological variances in the scribeline areas of a wafer adjacent to the dies. Surface features are used to reduce fracturing of molding compound and to prevent movement of the molding compound with respect to the surface of a die in a plastic encapsulated integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.