Dynamic memory cell using hollow post shape channel thin-film transistor
US5336917A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1992 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | Dec 4, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/373
Abstract
A semiconductor device comprises a first insulating layer, a gate electrode formed on the insulating layer, a second insulating layer formed on the gate electrode, an opening formed through the second insulating layer, the gate electrode and the first insulating layer, a gate insulating layer formed to overlay the inner surface of the opening, a monocrystalline silicon layer formed on the gate insulating layer within the opening to oppose the gate electrode, a monocrystalline silicon layer formed within the opening to make contact with the monocrystalline silicon layer and oppose the first insulating layer, and a monocrystalline silicon layer formed within the opening to make contact with the monocrystalline silicon layer and oppose the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.