Method and apparatus for power control in devices
US5337285A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1993 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | May 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.