Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
US5337415A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1992 |
| Grant date | Aug 9, 1994 |
| Priority date | — |
| Expiry date | Dec 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled. The bit information unit then transfers to cache bundle signals and instruction type signals. These signals are stored as predecode bits along with instructions from the instruction path in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.