Eric Delano
41Patents
15h-index
59Co-inventors
84Inventor score
Filing activity: Jul 12, 1991 → Apr 8, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5787494A | Software assisted hardware TLB miss handler | Physics | 96 | Expired |
| US5337415A | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency | Physics | 74 | Expired |
| US5603004A | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system | Physics | 64 | Expired |
| US7398374B2 | Multi-cluster processor for processing instructions of one or more instruction threads | Physics | 62 | Expired |
| US5493660A | Software assisted hardware TLB miss handler | Physics | 46 | Expired |
| US6049851A | Method and apparatus for checking cache coherency in a computer architecture | Physics | 42 | Expired |
| US6427188B1 | Method and system for early tag accesses for lower-level caches in parallel with first-level cache | Emerging Cross-Sectional Technologies | 35 | Expired |
| US5404496A | Computer-based system and method for debugging a computer system implementation | Physics | 31 | Expired |
| US5396604A | System and method for reducing the penalty associated with data cache misses | Physics | 25 | Expired |
| US7237144B2 | Off-chip lockstep checking | Physics | 24 | Expired |
| US7290169B2 | Core-level processor lockstepping | Physics | 22 | Expired |
| US7028167B2 | Core parallel execution with different optimization characteristics to decrease dynamic execution path | Physics | 22 | Expired |
| US6941489B2 | Checkpointing of register file | Physics | 19 | Expired |
| US5471602A | System and method of scoreboarding individual cache line segments | Physics | 18 | Expired |
| US7296181B2 | Lockstep error signaling | Physics | 15 | Expired |
| US8171121B2 | Method, system, and apparatus for dynamic reconfiguration of resources | Physics | 15 | Active |
| US7421689B2 | Processor-architecture for facilitating a virtual machine monitor | Physics | 15 | Active |
| US5617549A | System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer | Physics | 13 | Expired |
| US6931489B2 | Apparatus and methods for sharing cache among processors | Physics | 8 | Expired |
| US5526500A | System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions | Physics | 7 | Expired |
| US7734741B2 | Method, system, and apparatus for dynamic reconfiguration of resources | Physics | 6 | Active |
| US9183144B2 | Power gating a portion of a cache memory | Emerging Cross-Sectional Technologies | 5 | Active |
| US7930539B2 | Computer system resource access control | Physics | 5 | Active |
| US8219780B2 | Mitigating context switch cache miss penalty | Physics | 5 | Active |
| US9176875B2 | Power gating a portion of a cache memory | Emerging Cross-Sectional Technologies | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.