Method of forming a bit line over capacitor array of memory cells
US5338700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1993 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Apr 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a bit line over capacitor array of memory cells includes providing first conductive material pillars within first contact openings downwardly to active (source/drain) areas for ultimate connection with bit lines. A covering layer of insulating material is provided over the first pillars, and contact openings provided therethrough to electrically connect with other active (source/drain) areas for formation of capacitors. Capacitors are then provided within the capacitor contact openings. An overlying layer of insulating material is then provided over the covering layer of insulating material and over the capacitors. Bit line contact openings are then provided through the overlying layer and the covering layer to the first pillar upper surfaces. Then, a digit line layer of conductive material is provided atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.