Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures
US5338960A · kind A · utility
43Cited by
1References
28Claims
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Key dates
| Filing date | Aug 5, 1992 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Aug 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/615
Abstract
Dual polarity source/drain extensions are formed simultaneously in both PMOS and NMOS devices of a CMOS architecture using a common set of implants, so to be contiguous with one or both of source and drain regions of both the PMOS and the NMOS structures. The complementary conductivity lateral extension region configuration may be either an N over P or a P over N structure. The dual implant methodology can be carried out with no explicit masking steps, yielding MOS device which have source/drain extension regions that are self aligned to the gate and have minimal overlap capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.