Method for fabricating self-aligned epitaxial base transistor
US5340753A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1993 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Apr 14, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form the base layer. The present invention utilizes a thin very heavily doped LTE layer that is both a conductive etch stop and a diffusion source for doping the extrinsic base of the transistor. The deposition of the non-selective LTE base layer is followed immediately by the deposition of the conductive etch stop layer. A layer of undoped polycrystalline semiconductor is deposited on the conductive etch stop layer and subsequently ion implanted. Oxide and nitride insulating layers are deposited and the structure is patterned using a highly directional reactive ion etch to form the emitter window leaving a thin layer of the polycrystalline layer. The thin polycrystalline layer is selectively removed in a KOH solution leaving the conductive etch stop layer. The portion of the etch stop layer exposed in the emitter window is selectively removed by oxidation. Thereafter, conventional double polysilicon processing techniques are continued to form the insulator sidewalls and the emitter region in the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.