Method of manufacturing a vertical field effect transistor
US5340757A · kind A · utility
9Cited by
10References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 8, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Jul 8, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/831
Abstract
In the method of manufacturing a vertical field effect transistor, the gate region situated on either side of the source region projecting from a main face of a semiconductive substrate consists in implanting ions on either side of the source region to form a junction, and in forming a metal silicide on the gate region made in this way. Such a transistor is particularly suitable for being integrated in various MOS technologies, and in particular in CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.