Method of manufacturing EEPROM memory device
US5340760A · kind A · utility
34Cited by
0References
26Claims
0Family size
Inventors
Key dates
| Filing date | Dec 15, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Dec 15, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.