Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same
US5340763A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1993 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Feb 12, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides production repeatable process to form polysilicon storage node structures using MVP technology. The storage node is formed over word lines beginning with a deposition and planarization of an insulator or composite insulator. A contact/container photo and etch creates a contact/container opening to provide access to the underlying active area either directly or through a conductive plug. After the contact/container opening is formed, an insitu doped polysilicon layer is deposited and planarized to completely fill contact/container opening while isolating adjacent storage nodes from one another. Next an oxide layer is deposited and is followed by deposition of HSG poly. Then a plasma poly etch of the HSG poly is performed that is followed by a plasma oxide etch. After these steps, a timed poly etch is performed long enough to sufficiently transfer an `archipelago` pattern to storage node poly. Transferring of the `archipelago` pattern to poly produces very thin poly villus bars (or pins) to form a multi-pin storage node poly structure of the present invention. Finally a cell dielectric is deposited over the storage node poly and is followed by a deposit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.