Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon

US5340765A · kind A · utility

Assignee

• Micron Semiconductor, Inc. · US

Inventors

• Charles H. Dennison · San Jose, US
• Randhir P. S. Thakur · Boise, US

Key dates

• Filing date: Aug 13, 1993
• Grant date: Aug 23, 1994
• Expiry date: Aug 13, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/964

Abstract

The present invention develops a container capacitor by forming a conductively doped polysilicon plug between a pair of neighboring parallel conductive word lines; forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over the parallel conductive word lines and the plug; forming a planarized borophosphosilicate glass (BPSG) insulating layer over the planarized tetra-ethyl-ortho-silicate (TEOS) insulative layer; forming an opening into both insulating layers to expose an upper surface of the plug, the opening thereby forming a container shape; forming first, second and third layers of conductively doped amorphous silicon into the container shape while simultaneously bleeding oxygen into the amorphous silicon; forming individual container structures having inner and outer surfaces and thereby exposing the BPSG insulating layer; removing the BPSG insulating layer thereby exposing the outer surface of the container structures; converting the exposed inner and outer surfaces of amorphous silicon into hemispherical grained polysilicon by subjecting the structures to a high vacuum anneal; forming a nitride insulating layer adjacent and coextensive the conductive containe…