Method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays
US5341382A · kind A · utility
34Cited by
10References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 19, 1991 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Jun 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.