Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
US5341482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Dec 22, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition. The DRAIN instruction permits the source of the exception to be localized and permits the response to all arithmetic exceptions associated with instructions initiated before the DRAIN instruction, but identifi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.