Method for forming a vertical power MOSFET having doped oxide side wall spacers

US5342797A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Steven Sapp · Felton, US
• Neil Wylie · Abdulrahman Khaleefah Street, US
• Eugene Chen · Taipei, TW

Key dates

• Filing date: Nov 17, 1992
• Grant date: Aug 30, 1994
• Expiry date: Nov 17, 2012

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

A vertical power MOSFET comprising a metal base on which is disposed a highly doped n+ silicon substrate. A lightly doped epitaxial layer is grown on the substrate to form a drain region for conducting electrical charge carriers to the metal base. A gate region is disposed above the drain region and has side walls forming an aperture. Disposed on each side wall and axially aligned with the gate region are doped oxide spacers. Embedded within the source region beneath the aperture is a body region comprising a heavily doped region embedded within a lightly doped region. A source region, formed by diffusion from the doped oxide spacers, is disposed below each space and embedded within the body region.