Dense vertical programmable read only memory cell structure and processes for making them
US5343063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1990 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Dec 18, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.