Distributed memory architecture for a configurable logic array and method for using distributed memory
US5343406A · kind A · utility
291Cited by
19References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1989 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Jul 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.