Split-gate flash EEPROM cell and array with low voltage erasure
US5343424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1993 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Apr 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.