Memory having a latching BICMOS sense amplifier
US5343428A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1992 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Oct 5, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (80) having a latching BICMOS sense amplifier (20) includes a reduced power data retention mode. The latching BICMOS sense amplifier (20) senses and amplifies differential data signals corresponding to data from a selected memory cell (85). A latch (35) temporarily retains the logic state of the differential data signals in response to a clock signal. The reduced power data retention mode is provided by utilizing selectable current sources (66-75) responsive to an output enable signal. The latching BICMOS sense amplifier (20) allows for very high speed operation, yet provides for reduced power consumption while in a latched state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.