Harold Pilo
100Patents
16h-index
56Co-inventors
89Inventor score
Filing activity: Oct 5, 1992 → Sep 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5666078A | Programmable impedance output driver | Electricity | 164 | Expired |
| US6208572A | Semiconductor memory device having resistive bitline contact testing | Physics | 64 | Expired |
| US6219288A | Memory having user programmable AC timings | Physics | 51 | Expired |
| US6134182A | Cycle independent data to echo clock tracking circuit | Physics | 47 | Expired |
| US6133749A | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance | Electricity | 40 | Expired |
| US8363453B2 | Static random access memory (SRAM) write assist circuit with leakage suppression and level control | Physics | 37 | Active |
| US8233342B2 | Apparatus and method for implementing write assist for static random access memory arrays | Physics | 35 | Active |
| US6754135B2 | Reduced latency wide-I/O burst architecture | Physics | 31 | Expired |
| US7643357B2 | System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture | Physics | 29 | Active |
| US8279687B2 | Single supply sub VDD bit-line precharge SRAM and method for level shifting | Physics | 28 | Active |
| US6509778B2 | BIST circuit for variable impedance system | Physics | 26 | Expired |
| US5343428A | Memory having a latching BICMOS sense amplifier | Physics | 21 | Expired |
| US9123439B2 | SRAM write-assisted operation with VDD-to-VCS level shifting | Physics | 17 | Active |
| US7724565B2 | Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices | Physics | 17 | Active |
| US7904658B2 | Structure for power-efficient cache memory | Emerging Cross-Sectional Technologies | 16 | Active |
| US5659508A | Special mode enable transparent to normal mode operation | Physics | 16 | Expired |
| US6038181A | Efficient semiconductor burn-in circuit and method of operation | Physics | 16 | Expired |
| US6400629B1 | System and method for early write to memory by holding bitline at fixed potential | Physics | 14 | Expired |
| US8233337B2 | SRAM delay circuit that tracks bitcell characteristics | Physics | 13 | Active |
| US7613050B2 | Sense-amplifier assist (SAA) with power-reduction technique | Physics | 13 | Active |
| US5978929A | Computer unit responsive to difference between external clock period and circuit characteristic period | Physics | 13 | Expired |
| US6967861B2 | Method and apparatus for improving cycle time in a quad data rate SRAM device | Physics | 11 | Expired |
| US7817481B2 | Column selectable self-biasing virtual voltages for SRAM write assist | Physics | 11 | Active |
| US6999547B2 | Delay-lock-loop with improved accuracy and range | Electricity | 10 | Expired |
| US8027207B2 | Leakage compensated reference voltage generation system | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.