CMOS sense amplifier
US5343433A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1990 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Jul 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.