Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate
US5344785A · kind A · utility
37Cited by
28References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1993 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | Jun 3, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.