Method for generating power slits
US5345394A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1992 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | Feb 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90.degree. angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.