Method of integrated circuit chips design
US5347465A · kind A · utility
21Cited by
14References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1992 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | May 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.