Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
US5347489A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1992 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Apr 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3477
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.