Nonvolatile semiconductor memory device
US5347490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1991 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Jun 10, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.