Enhancement circuit and method for ensuring diactuation of a switching device
US5349247A · kind A · utility
27Cited by
21References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1992 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Jun 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current. The invention is an enhancement circuit for ensuring the deactuation of the pull-down portion of the push-pull arrangement during the action of the CMOS transistor arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.