Multiple clock rate test apparatus for testing digital systems
US5349587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1992 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Mar 26, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.