Digital serializer and time delay regulator
US5349612A · kind A · utility
59Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1992 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Jun 19, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A self calibrated time delay circuit including a plurality of serially connected unit delay cells each having an output tap which is selectable, a registration means for simultaneously determining the status of each output node of each of the unit delay cells, combinatorial and sequential logic units for analyzing said registration means and sending error correction commands to an up/down controller, said up down controller providing a command code for controlling the delay of each said unit delay by selecting which tap is output from said unit delay cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.