System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation
US5349651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1991 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Aug 9, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addres…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.