Low resistance silicided substrate contact
US5350942A · kind A · utility
3Cited by
13References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1993 |
| Grant date | Sep 27, 1994 |
| Priority date | — |
| Expiry date | Aug 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.