Signed two's complement constant multiplier compiler
US5351206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1992 |
| Grant date | Sep 27, 1994 |
| Priority date | — |
| Expiry date | Nov 12, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A constant multiplier compiler model allows a signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. For each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.