Method of making semiconductor device with memory cells and peripheral transistors

US5352620A · kind A · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Kazuhiro Komori · Higashikurume, JP
• Kenichi Kuroda · Tokyo, JP
• June Sugiura · Musashino, JP

Key dates

• Filing date: Jun 2, 1993
• Grant date: Oct 4, 1994
• Expiry date: Jun 2, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.