Hardware modeling system and method of use
US5353243A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1992 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Aug 31, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31928
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five st…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.