Memory integrated circuit with balanced resistance
US5353245A · kind A · utility
10Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1993 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Aug 24, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
An integrated circuit, illustratively an SRAM, with pull down gates symmetrically positioned with respect to the ground line is disclosed. The symmetric positioning helps to insure cell stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.